An information processing system is proposed which prefetches an interrupt service program to a prefetch buffer during a period when an interrupt request to a processor, such as a CPU, is generated until the processor starts to execute the interrupt service program. Moreover, in an information processing system wherein an interrupt processing regularly occurs, an approach to transfer data for use in the interrupt processing to a cache memory in advance is proposed. Related arts are discussed in Japanese Laid-open Patent Publication No. 08-221270 and No. 2004-252729.
The value in a register of an I/O device or the like for use in the interrupt processing varies also depending on factors other than the rewrite by the program. On the other hand, the data in the cache memory may be held over a long period until the data is driven out. For this reason, even if the data held in the register of the I/O device or the like is held in the cache memory, it may not guarantee that the value in the register and the value held in the cache memory are the same. That is, in the above-described interrupt service program, although the cache memory may be prefetched, the data held in the register of the I/O device or the like may not be prefetched to the cache memory. Therefore, in the interrupt service program, the register of the I/O device or the like may need to be directly accessed. Since the I/O device or the like is usually coupled to a low-speed slave port, the direct access to the register of the I/O device or the like degrades the execution efficiency of the interrupt service program and degrades the performance of the information processing system.